Oliver Walter 84d6be2bde added stlink serial for test setup

2024-02-08 02:46:20 +01:00

.vscode

added stlink serial for test setup

2024-02-08 02:46:20 +01:00

Application

existing FW file check to avoid redundant transmit

2024-02-08 02:44:26 +01:00

cmake

Initial setup

2024-02-01 21:31:10 +01:00

cmake_generated

added minmal libaries

2024-02-02 02:44:24 +01:00

Core

turn on CLS relay on boot

2024-02-08 02:45:34 +01:00

Drivers

Initial setup

2024-02-01 21:31:10 +01:00

FATFS

added minmal libaries

2024-02-02 02:44:24 +01:00

lib

added minmal libaries

2024-02-02 02:44:24 +01:00

Middlewares

Initial setup

2024-02-01 21:31:10 +01:00

proto

existing FW file check to avoid redundant transmit

2024-02-08 02:44:26 +01:00

tests

update cls

2024-02-06 03:24:43 +01:00

tools

implenet new fwUp behaviour in py

2024-02-08 02:45:09 +01:00

USB_DEVICE

First Draft of the UsbDataHandler

2024-02-02 03:58:09 +01:00

.clang-format

added clang-format style

2024-02-02 19:54:16 +01:00

.cproject

Initial setup

2024-02-01 21:31:10 +01:00

.gitignore

set CLS CAN to 500kbit

2024-02-05 14:22:56 +01:00

.gitmodules

Added CLS as a submodule

2024-02-05 19:51:38 +01:00

.mxproject

update cubeMX FDCAN1

2024-02-04 17:14:57 +01:00

.project

Initial setup

2024-02-01 21:31:10 +01:00

CLS_Master.ioc

set CLS CAN to 500kbit

2024-02-05 14:22:56 +01:00

CMakeLists.txt

make libCLS more independen of HW

2024-02-05 19:46:48 +01:00

CMakePresets.json

Initial setup

2024-02-01 21:31:10 +01:00

README_how_to_build.md

Initial setup

2024-02-01 21:31:10 +01:00

stm32h7x3i_eval.cfg

added openocd confiig

2024-02-05 14:21:55 +01:00

STM32H723.svd

Initial setup

2024-02-01 21:31:10 +01:00

STM32H723VGTX_FLASH.ld

fixed some LTO issues

2024-02-02 19:54:04 +01:00

STM32H723VGTX_RAM.ld

Initial setup

2024-02-01 21:31:10 +01:00

Description

No description provided

2.4 MiB

Languages

C 99.3%

Assembly 0.3%

CMake 0.2%

Python 0.2%