547 lines
20 KiB
C
547 lines
20 KiB
C
/*
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* This example shows how application can implement RX and TX DMA for UART.
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* It uses simple packet example approach and 3 separate buffers:
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*
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* - Raw DMA RX buffer where DMA transfers data from UART to memory
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* - Ringbuff for RX data which are transfered from raw buffer and ready for application processin
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* - Ringbuff for TX data to be sent out by DMA TX
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*/
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/* Includes */
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#include "main.h"
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include "lwrb.h"
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/* Private function prototypes */
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void SystemClock_Config(void);
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/* USART related functions */
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void usart_init(void);
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void usart_rx_check(void);
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void usart_process_data(const void* data, size_t len);
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void usart_send_string(const char* str);
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uint8_t usart_start_tx_dma_transfer(void);
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/**
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* \brief Calculate length of statically allocated array
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*/
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#define ARRAY_LEN(x) (sizeof(x) / sizeof((x)[0]))
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/**
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* \brief USART RX buffer for DMA to transfer every received byte RX
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* \note Contains raw data that are about to be processed by different events
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*
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* Special use case for STM32H7 series.
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* Default memory configuration in STM32H7 may put variables to DTCM RAM,
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* part of memory that is super fast, however DMA has no access to it.
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*
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* For this specific example, all variables are by default
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* configured in D1 RAM. This is configured in linker script
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*/
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uint8_t
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usart_rx_dma_buffer[64];
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/**
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* \brief Ring buffer instance for TX data
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*/
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lwrb_t
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usart_rx_rb;
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/**
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* \brief Ring buffer data array for RX DMA
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*/
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uint8_t
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usart_rx_rb_data[128];
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/**
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* \brief Ring buffer instance for TX data
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*/
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lwrb_t
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usart_tx_rb;
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/**
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* \brief Ring buffer data array for TX DMA
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*/
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uint8_t
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usart_tx_rb_data[128];
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/**
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* \brief Length of currently active TX DMA transfer
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*/
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volatile size_t
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usart_tx_dma_current_len;
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/**
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* \brief Application entry point
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*/
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int
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main(void) {
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uint8_t state, cmd, len;
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/* MCU Configuration */
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// SCB_DisableDCache();
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// SCB_DisableICache();
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/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
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LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG);
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/* Configure the system clock */
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SystemClock_Config();
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/* Initialize ringbuff for TX & RX */
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lwrb_init(&usart_tx_rb, usart_tx_rb_data, sizeof(usart_tx_rb_data));
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lwrb_init(&usart_rx_rb, usart_rx_rb_data, sizeof(usart_rx_rb_data));
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/* Initialize all configured peripherals */
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usart_init();
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usart_send_string("USART DMA example: DMA HT & TC + USART IDLE LINE interrupts\r\n");
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usart_send_string("Start sending data to STM32\r\n");
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/* After this point, do not use usart_send_string function anymore */
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/* Send packet data over UART from PC (or other STM32 device) */
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/* Infinite loop */
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state = 0;
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while (1) {
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uint8_t b;
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/* Process RX ringbuffer */
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/* Packet format: START_BYTE, CMD, LEN[, DATA[0], DATA[len - 1]], STOP BYTE */
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/* DATA bytes are included only if LEN > 0 */
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/* An example, send sequence of these bytes: 0x55, 0x01, 0x01, 0xFF, 0xAA */
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/* Read byte by byte */
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if (lwrb_read(&usart_rx_rb, &b, 1) == 1) {
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lwrb_write(&usart_tx_rb, &b, 1); /* Write data to transmit buffer */
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usart_start_tx_dma_transfer();
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switch (state) {
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case 0: { /* Wait for start byte */
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if (b == 0x55) {
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++state;
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}
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break;
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}
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case 1: { /* Check packet command */
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cmd = b;
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++state;
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break;
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}
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case 2: { /* Packet data length */
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len = b;
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++state;
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if (len == 0) {
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++state; /* Ignore data part if len = 0 */
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}
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break;
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}
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case 3: { /* Data for command */
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--len; /* Decrease for received character */
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if (len == 0) {
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++state;
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}
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break;
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}
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case 4: { /* End of packet */
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if (b == 0xAA) {
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/* Packet is valid */
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/* Send out response with CMD = 0xFF */
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b = 0x55; /* Start byte */
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lwrb_write(&usart_tx_rb, &b, 1);
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cmd = 0xFF; /* Command = 0xFF = OK response */
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lwrb_write(&usart_tx_rb, &cmd, 1);
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b = 0x00; /* Len = 0 */
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lwrb_write(&usart_tx_rb, &b, 1);
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b = 0xAA; /* Stop byte */
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lwrb_write(&usart_tx_rb, &b, 1);
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/* Flush everything */
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usart_start_tx_dma_transfer();
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}
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state = 0;
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break;
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}
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}
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}
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/* Do other tasks ... */
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}
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}
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/**
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* \brief Check for new data received with DMA
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*
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* User must select context to call this function from:
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* - Only interrupts (DMA HT, DMA TC, UART IDLE) with same preemption priority level
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* - Only thread context (outside interrupts)
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*
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* If called from both context-es, exclusive access protection must be implemented
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* This mode is not advised as it usually means architecture design problems
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*
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* When IDLE interrupt is not present, application must rely only on thread context,
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* by manually calling function as quickly as possible, to make sure
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* data are read from raw buffer and processed.
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*
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* Not doing reads fast enough may cause DMA to overflow unread received bytes,
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* hence application will lost useful data.
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*
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* Solutions to this are:
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* - Improve architecture design to achieve faster reads
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* - Increase raw buffer size and allow DMA to write more data before this function is called
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*/
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void
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usart_rx_check(void) {
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static size_t old_pos;
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size_t pos;
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/* Calculate current position in buffer and check for new data available */
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pos = ARRAY_LEN(usart_rx_dma_buffer) - LL_DMA_GetDataLength(DMA1, LL_DMA_STREAM_0);
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if (pos != old_pos) { /* Check change in received data */
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if (pos > old_pos) { /* Current position is over previous one */
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/*
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* Processing is done in "linear" mode.
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*
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* Application processing is fast with single data block,
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* length is simply calculated by subtracting pointers
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*
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* [ 0 ]
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* [ 1 ] <- old_pos |------------------------------------|
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* [ 2 ] | |
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* [ 3 ] | Single block (len = pos - old_pos) |
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* [ 4 ] | |
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* [ 5 ] |------------------------------------|
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* [ 6 ] <- pos
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* [ 7 ]
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* [ N - 1 ]
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*/
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usart_process_data(&usart_rx_dma_buffer[old_pos], pos - old_pos);
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} else {
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/*
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* Processing is done in "overflow" mode..
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*
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* Application must process data twice,
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* since there are 2 linear memory blocks to handle
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*
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* [ 0 ] |---------------------------------|
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* [ 1 ] | Second block (len = pos) |
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* [ 2 ] |---------------------------------|
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* [ 3 ] <- pos
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* [ 4 ] <- old_pos |---------------------------------|
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* [ 5 ] | |
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* [ 6 ] | First block (len = N - old_pos) |
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* [ 7 ] | |
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* [ N - 1 ] |---------------------------------|
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*/
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usart_process_data(&usart_rx_dma_buffer[old_pos], ARRAY_LEN(usart_rx_dma_buffer) - old_pos);
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if (pos > 0) {
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usart_process_data(&usart_rx_dma_buffer[0], pos);
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}
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}
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old_pos = pos; /* Save current position as old for next transfers */
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}
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}
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/**
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* \brief Check if DMA is active and if not try to send data
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*
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* This function can be called either by application to start data transfer
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* or from DMA TX interrupt after previous transfer just finished
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*
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* \return `1` if transfer just started, `0` if on-going or no data to transmit
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*/
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uint8_t
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usart_start_tx_dma_transfer(void) {
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uint32_t primask;
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uint8_t started = 0;
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/*
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* First check if transfer is currently in-active,
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* by examining the value of usart_tx_dma_current_len variable.
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*
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* This variable is set before DMA transfer is started and cleared in DMA TX complete interrupt.
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*
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* It is not necessary to disable the interrupts before checking the variable:
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*
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* When usart_tx_dma_current_len == 0
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* - This function is called by either application or TX DMA interrupt
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* - When called from interrupt, it was just reset before the call,
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* indicating transfer just completed and ready for more
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* - When called from an application, transfer was previously already in-active
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* and immediate call from interrupt cannot happen at this moment
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*
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* When usart_tx_dma_current_len != 0
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* - This function is called only by an application.
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* - It will never be called from interrupt with usart_tx_dma_current_len != 0 condition
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*
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* Disabling interrupts before checking for next transfer is advised
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* only if multiple operating system threads can access to this function w/o
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* exclusive access protection (mutex) configured,
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* or if application calls this function from multiple interrupts.
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*
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* This example assumes worst use case scenario,
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* hence interrupts are disabled prior every check
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*/
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primask = __get_PRIMASK();
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__disable_irq();
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if (usart_tx_dma_current_len == 0
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&& (usart_tx_dma_current_len = lwrb_get_linear_block_read_length(&usart_tx_rb)) > 0) {
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/* Disable channel if enabled */
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LL_DMA_DisableStream(DMA1, LL_DMA_STREAM_1);
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/* Clear all flags */
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LL_DMA_ClearFlag_TC1(DMA1);
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LL_DMA_ClearFlag_HT1(DMA1);
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LL_DMA_ClearFlag_TE1(DMA1);
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LL_DMA_ClearFlag_DME1(DMA1);
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LL_DMA_ClearFlag_FE1(DMA1);
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/* Prepare DMA data and length */
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LL_DMA_SetDataLength(DMA1, LL_DMA_STREAM_1, usart_tx_dma_current_len);
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LL_DMA_SetMemoryAddress(DMA1, LL_DMA_STREAM_1, (uint32_t)lwrb_get_linear_block_read_address(&usart_tx_rb));
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/* Start transfer */
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LL_DMA_EnableStream(DMA1, LL_DMA_STREAM_1);
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started = 1;
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}
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__set_PRIMASK(primask);
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return started;
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}
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/**
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* \brief Process received data over UART
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* Data are written to RX ringbuffer for application processing at latter stage
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* \param[in] data: Data to process
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* \param[in] len: Length in units of bytes
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*/
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void
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usart_process_data(const void* data, size_t len) {
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lwrb_write(&usart_rx_rb, data, len); /* Write data to receive buffer */
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}
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/**
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* \brief Send string over USART
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* \param[in] str: String to send
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*/
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void
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usart_send_string(const char* str) {
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lwrb_write(&usart_tx_rb, str, strlen(str)); /* Write data to transmit buffer */
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usart_start_tx_dma_transfer();
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}
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/**
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* \brief USART3 Initialization Function
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*/
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void
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usart_init(void) {
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LL_USART_InitTypeDef USART_InitStruct = {0};
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// CUBE_MX does this already
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//LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
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/* Peripheral clock enable */
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//LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART3);
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//LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOD);
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//LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
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/*
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* USART3 GPIO Configuration
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*
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* PD8 ------> USART3_TX
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* PD9 ------> USART3_RX
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*/
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//GPIO_InitStruct.Pin = LL_GPIO_PIN_8 | LL_GPIO_PIN_9;
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//GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
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//GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH;
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//GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
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//GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
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//GPIO_InitStruct.Alternate = LL_GPIO_AF_7;
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//LL_GPIO_Init(GPIOD, &GPIO_InitStruct);
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/* USART3_RX Init */
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// CUBE_MX does this already
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//LL_DMA_SetPeriphRequest(DMA1, LL_DMA_STREAM_0, LL_DMAMUX1_REQ_USART3_RX);
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//LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_STREAM_0, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
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//LL_DMA_SetStreamPriorityLevel(DMA1, LL_DMA_STREAM_0, LL_DMA_PRIORITY_LOW);
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//LL_DMA_SetMode(DMA1, LL_DMA_STREAM_0, LL_DMA_MODE_CIRCULAR);
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//LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_STREAM_0, LL_DMA_PERIPH_NOINCREMENT);
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//LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_STREAM_0, LL_DMA_MEMORY_INCREMENT);
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//LL_DMA_SetPeriphSize(DMA1, LL_DMA_STREAM_0, LL_DMA_PDATAALIGN_BYTE);
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//LL_DMA_SetMemorySize(DMA1, LL_DMA_STREAM_0, LL_DMA_MDATAALIGN_BYTE);
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//LL_DMA_DisableFifoMode(DMA1, LL_DMA_STREAM_0);
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LL_DMA_SetPeriphAddress(DMA1, LL_DMA_STREAM_0, LL_USART_DMA_GetRegAddr(USART3, LL_USART_DMA_REG_DATA_RECEIVE));
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LL_DMA_SetMemoryAddress(DMA1, LL_DMA_STREAM_0, (uint32_t)usart_rx_dma_buffer);
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LL_DMA_SetDataLength(DMA1, LL_DMA_STREAM_0, ARRAY_LEN(usart_rx_dma_buffer));
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/* USART3_TX Init */
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// CUBE_MX does this already
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//LL_DMA_SetPeriphRequest(DMA1, LL_DMA_STREAM_1, LL_DMAMUX1_REQ_USART3_TX);
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//LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_STREAM_1, LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
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//LL_DMA_SetStreamPriorityLevel(DMA1, LL_DMA_STREAM_1, LL_DMA_PRIORITY_LOW);
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//LL_DMA_SetMode(DMA1, LL_DMA_STREAM_1, LL_DMA_MODE_NORMAL);
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//LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_STREAM_1, LL_DMA_PERIPH_NOINCREMENT);
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//LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_STREAM_1, LL_DMA_MEMORY_INCREMENT);
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//LL_DMA_SetPeriphSize(DMA1, LL_DMA_STREAM_1, LL_DMA_PDATAALIGN_BYTE);
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//LL_DMA_SetMemorySize(DMA1, LL_DMA_STREAM_1, LL_DMA_MDATAALIGN_BYTE);
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//LL_DMA_DisableFifoMode(DMA1, LL_DMA_STREAM_1);
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LL_DMA_SetPeriphAddress(DMA1, LL_DMA_STREAM_1, LL_USART_DMA_GetRegAddr(USART3, LL_USART_DMA_REG_DATA_TRANSMIT));
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/* Enable DMA RX HT & TC interrupts */
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LL_DMA_EnableIT_HT(DMA1, LL_DMA_STREAM_0);
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LL_DMA_EnableIT_TC(DMA1, LL_DMA_STREAM_0);
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/* Enable DMA TX TC interrupts */
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LL_DMA_EnableIT_TC(DMA1, LL_DMA_STREAM_1);
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/* DMA interrupt init */
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// CUBE_MX does this already dma.c
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//NVIC_SetPriority(DMA1_Stream0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
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//NVIC_EnableIRQ(DMA1_Stream0_IRQn);
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//NVIC_SetPriority(DMA1_Stream1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
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//NVIC_EnableIRQ(DMA1_Stream1_IRQn);
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/* Configure USART3 */
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// CUBE_MX does this already usart.c
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//USART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1;
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//USART_InitStruct.BaudRate = 115200;
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//USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B;
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//USART_InitStruct.StopBits = LL_USART_STOPBITS_1;
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//USART_InitStruct.Parity = LL_USART_PARITY_NONE;
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//USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;
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//USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;
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//USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;
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//LL_USART_Init(USART3, &USART_InitStruct);
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//LL_USART_SetTXFIFOThreshold(USART3, LL_USART_FIFOTHRESHOLD_7_8);
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//LL_USART_SetRXFIFOThreshold(USART3, LL_USART_FIFOTHRESHOLD_7_8);
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//LL_USART_EnableFIFO(USART3);
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//LL_USART_ConfigAsyncMode(USART3);
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LL_USART_EnableDMAReq_RX(USART3);
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LL_USART_EnableDMAReq_TX(USART3);
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LL_USART_EnableIT_IDLE(USART3);
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/* USART interrupt, same priority as DMA channel */
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// CUBE_MX does this already usart.c
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//NVIC_SetPriority(USART3_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
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//NVIC_EnableIRQ(USART3_IRQn);
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/* Enable USART and DMA RX */
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LL_DMA_EnableStream(DMA1, LL_DMA_STREAM_0);
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//LL_USART_Enable(USART3);
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/* Polling USART3 initialization */
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while (!LL_USART_IsActiveFlag_TEACK(USART3) || !LL_USART_IsActiveFlag_REACK(USART3)) {}
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}
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/* Interrupt handlers here */
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/**
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* \brief DMA1 stream1 interrupt handler for USART3 RX
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*/
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void
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DMA1_Stream0_IRQHandler(void) {
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/* Check half-transfer complete interrupt */
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if (LL_DMA_IsEnabledIT_HT(DMA1, LL_DMA_STREAM_0) && LL_DMA_IsActiveFlag_HT0(DMA1)) {
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LL_DMA_ClearFlag_HT0(DMA1); /* Clear half-transfer complete flag */
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usart_rx_check(); /* Check for data to process */
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}
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/* Check transfer-complete interrupt */
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if (LL_DMA_IsEnabledIT_TC(DMA1, LL_DMA_STREAM_0) && LL_DMA_IsActiveFlag_TC0(DMA1)) {
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LL_DMA_ClearFlag_TC0(DMA1); /* Clear transfer complete flag */
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usart_rx_check(); /* Check for data to process */
|
|
}
|
|
|
|
/* Implement other events when needed */
|
|
}
|
|
|
|
/**
|
|
* \brief DMA1 stream1 interrupt handler for USART3 TX
|
|
*/
|
|
void
|
|
DMA1_Stream1_IRQHandler(void) {
|
|
/* Check transfer complete */
|
|
if (LL_DMA_IsEnabledIT_TC(DMA1, LL_DMA_STREAM_1) && LL_DMA_IsActiveFlag_TC1(DMA1)) {
|
|
LL_DMA_ClearFlag_TC1(DMA1); /* Clear transfer complete flag */
|
|
lwrb_skip(&usart_tx_rb, usart_tx_dma_current_len);/* Skip sent data, mark as read */
|
|
usart_tx_dma_current_len = 0; /* Clear length variable */
|
|
usart_start_tx_dma_transfer(); /* Start sending more data */
|
|
}
|
|
|
|
/* Implement other events when needed */
|
|
}
|
|
|
|
/**
|
|
* \brief USART3 global interrupt handler
|
|
*/
|
|
void
|
|
USART3_IRQHandler(void) {
|
|
/* Check for IDLE line interrupt */
|
|
if (LL_USART_IsEnabledIT_IDLE(USART3) && LL_USART_IsActiveFlag_IDLE(USART3)) {
|
|
LL_USART_ClearFlag_IDLE(USART3); /* Clear IDLE line flag */
|
|
usart_rx_check(); /* Check for data to process */
|
|
}
|
|
|
|
/* Implement other events when needed */
|
|
}
|
|
|
|
/**
|
|
* \brief System Clock Configuration
|
|
*/
|
|
void
|
|
SystemClock_Config(void) {
|
|
/* Configure flash latency */
|
|
LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
|
|
if (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_4) {
|
|
while (1) {}
|
|
}
|
|
|
|
/* Configure power supply and voltage scale */
|
|
LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
|
|
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
|
|
|
|
/* Uncomment if used on STM32H745/H755 Nucleo */
|
|
/* Dual-Core Nucleo board used external SMPS instead of LDO */
|
|
/* Manually enable it */
|
|
//PWR->CR3 |= 1 << 2;
|
|
|
|
/* Configure HSE */
|
|
LL_RCC_HSE_EnableBypass();
|
|
LL_RCC_HSE_Enable();
|
|
while (!LL_RCC_HSE_IsReady()) {}
|
|
|
|
/* Configure PLL */
|
|
LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
|
|
LL_RCC_PLL1P_Enable();
|
|
LL_RCC_PLL1Q_Enable();
|
|
LL_RCC_PLL1_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_8_16);
|
|
LL_RCC_PLL1_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE);
|
|
LL_RCC_PLL1_SetM(1);
|
|
LL_RCC_PLL1_SetN(120);
|
|
LL_RCC_PLL1_SetP(2);
|
|
LL_RCC_PLL1_SetQ(20);
|
|
LL_RCC_PLL1_SetR(2);
|
|
LL_RCC_PLL1_Enable();
|
|
while (!LL_RCC_PLL1_IsReady()) {}
|
|
|
|
/* Intermediate AHB prescaler 2 when target frequency clock is higher than 80 MHz */
|
|
LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2);
|
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
|
|
LL_RCC_SetSysPrescaler(LL_RCC_SYSCLK_DIV_1);
|
|
LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2);
|
|
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);
|
|
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);
|
|
LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_2);
|
|
LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_2);
|
|
|
|
/* Configure systick */
|
|
LL_Init1msTick(480000000);
|
|
LL_SYSTICK_SetClkSource(LL_SYSTICK_CLKSOURCE_HCLK);
|
|
LL_SetSystemCoreClock(480000000);
|
|
LL_RCC_SetUSARTClockSource(LL_RCC_USART234578_CLKSOURCE_PCLK1);
|
|
}
|