Oliver Walter
ddfda14085
Makes end-to-end verification of the bus possible with a spare RP2040 and no dedicated RS485 dongle. bridge/ turns a second Pico into a transparent USB-to-RS485 bridge. It is deliberately protocol-agnostic: bytes from USB go out on the pair, bytes from the pair go back up USB, and it knows nothing about frames, addresses or CRCs. A protocol-aware bridge could have a bug that happens to agree with the node's own, which would defeat the point of using it as a test instrument. It also needs no register-level code — it never has to delimit a frame, and the one thing it does need, knowing that the final stop bit has cleared the shifter before releasing DE, rp2040-hal exposes as uart_is_busy(). tools/wiredsensor.py is an independent implementation of the wire format, written from the specification in README.md rather than sharing code with wiredsensor-core. Shared code would let a framing or CRC bug cancel out and every test pass regardless. Cross-checked: it reproduces the CRC-16/MODBUS catalogue vector and builds byte-identical frames to the Rust side for all five documented examples. Its `test` subcommand covers what host tests structurally cannot, all of it timing-dependent: that malformed and mis-addressed frames leave the node silent rather than colliding with whoever was actually addressed, that the driver-enable turnaround leaves replies intact, and that no state leaks between back-to-back frames. Uses one wiring diagram for both boards, since the bridge mirrors the node's GPIO0/1/2 assignment. Frames must fit one 64-byte USB packet, as each host write becomes exactly one DE-bracketed transmission; every real command is at most 21 bytes. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
22 lines
608 B
Plaintext
22 lines
608 B
Plaintext
/* RP2040 with 2 MiB of QSPI flash.
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*
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* The boot ROM reads the first 256 bytes of flash into RAM and executes them to
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* bring up XIP, so .boot2 must sit at the very start and the vector table must
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* follow immediately after it. */
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MEMORY {
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BOOT2 : ORIGIN = 0x10000000, LENGTH = 0x100
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FLASH : ORIGIN = 0x10000100, LENGTH = 2048K - 0x100
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/* The four 64 KiB SRAM banks are striped, so treat them as one region. */
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RAM : ORIGIN = 0x20000000, LENGTH = 256K
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}
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EXTERN(BOOT2_FIRMWARE)
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SECTIONS {
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.boot2 ORIGIN(BOOT2) :
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{
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KEEP(*(.boot2));
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} > BOOT2
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} INSERT BEFORE .text;
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