Oliver Walter
ddfda14085
Makes end-to-end verification of the bus possible with a spare RP2040 and no dedicated RS485 dongle. bridge/ turns a second Pico into a transparent USB-to-RS485 bridge. It is deliberately protocol-agnostic: bytes from USB go out on the pair, bytes from the pair go back up USB, and it knows nothing about frames, addresses or CRCs. A protocol-aware bridge could have a bug that happens to agree with the node's own, which would defeat the point of using it as a test instrument. It also needs no register-level code — it never has to delimit a frame, and the one thing it does need, knowing that the final stop bit has cleared the shifter before releasing DE, rp2040-hal exposes as uart_is_busy(). tools/wiredsensor.py is an independent implementation of the wire format, written from the specification in README.md rather than sharing code with wiredsensor-core. Shared code would let a framing or CRC bug cancel out and every test pass regardless. Cross-checked: it reproduces the CRC-16/MODBUS catalogue vector and builds byte-identical frames to the Rust side for all five documented examples. Its `test` subcommand covers what host tests structurally cannot, all of it timing-dependent: that malformed and mis-addressed frames leave the node silent rather than colliding with whoever was actually addressed, that the driver-enable turnaround leaves replies intact, and that no state leaks between back-to-back frames. Uses one wiring diagram for both boards, since the bridge mirrors the node's GPIO0/1/2 assignment. Frames must fit one 64-byte USB packet, as each host write becomes exactly one DE-bracketed transmission; every real command is at most 21 bytes. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
32 lines
718 B
TOML
32 lines
718 B
TOML
[workspace]
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resolver = "2"
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members = ["core", "firmware", "bridge"]
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[workspace.package]
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version = "0.1.0"
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edition = "2021"
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license = "MIT OR Apache-2.0"
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[workspace.dependencies]
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wiredsensor-core = { path = "core" }
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defmt = "1.1"
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# Cortex-M0+ has no hardware divide and a small cache-less flash path, so even
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# debug builds want size optimisation or timing-sensitive paths get sloppy.
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[profile.dev]
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codegen-units = 1
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debug = 2
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debug-assertions = true
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incremental = false
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opt-level = "s"
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overflow-checks = true
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[profile.release]
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codegen-units = 1
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debug = 2 # keep DWARF for probe-rs/defmt; it is not flashed
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debug-assertions = false
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incremental = false
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lto = "fat"
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opt-level = "s"
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overflow-checks = false
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